1. Field of the Invention
This invention relates to a method of doping the polysilicon gates of a CMOS device, specifically the PMOS gate, having thin gate oxide and gate regions.
2. Brief Description of the Prior Art
In the formation of semiconductor devices and primarily logic devices, dual work function polycrystalline silicon (polysilicon) is becoming increasingly common in CMOS processing for enhanced PMOS performance. A goal is to provide high performance CMOS devices wherein both the NMOS transistor and the PMOS transistor are surface channel with symmetric threshold voltages. In such devices, it is necessary that the polysilicon gate of the NMOS transistor be doped n-type and that the polysilicon gate of the PMOS transistor be doped p-type. It is known that, when a true metal is used for the gate material, there is an almost unlimited (relative to actual requirements) supply of free carriers and gate depletion is therefore not a problem. On the other hand, when heavily doped polysilicon is used as the gate material, it acts as a semi-metal but can present a depletion problem. Under a bias sufficient to invert the channel on the other side of the gate oxide, free electrons or holes (depending on conductivity type) will move away from the polysilicon/oxide interface, making the gate oxide electrically thicker than it is physically and decreasing the drive current. Accordingly, adequately doping the PMOS gates has been recognized by the industry to be a challenging problem. Boron is the only reasonable dopant for the task and boron presents several problems. B(11), the most common implanted boron species, has significant straggle into the polysilicon as-implanted, forcing use of a very low implant energy to prevent penetration of the end of the projected range through the gate oxide during boron implant. Switching to BF.sub.2 as the dopant can provide a shallower implant and eliminate much of the straggle, however adding of fluorine in the polysilicon enhances boron penetration of the polysilicon gate during gate dopant activation.
Achieving uniform dopant distribution and activation in the P+ gates without having the boron penetrate the gate oxide is a serious problem. Low concentration at the polysilicon gate/gate oxide interface can lead to polysilicon depletion under channel inversion biasing, resulting in a thicker effective gate oxide and lower drive current. Boron penetration of the PMOS gate oxides results in unacceptable transition voltage (V.sub.t) shifts and poor site to site transistor performance uniformity.
The industry has directed a great deal of attention to the above noted problems. Some approaches concentrate upon changing the polysilicon physical structure as discussed in "Improving gate oxide integrity in p+p MOSFET by using large grain size polysilicon gate", M. Koda et al., 1993 IEDM Technical Digest, page 471, or layering the gate electrode to reduce the boron diffusivity as discussed in "Suppression of Boron Penetration into an Ultra-Thin Gate Oxide by Using a Stacked-Amorphous-Silicon Film", S. Wu et al., 1993 IEDM Technical Digest, page 329. Others change the composition of the gate oxide to make it a better boron diffusion barrier as discussed in "A Boron-Retarding and High Interface Quality Thin Gate Dielectric for Deep-Submicron Devices", L. Manchanda et al., 1993 IEDM Technical Digest, page 459. All of the above described approaches either add process complexity or do not fully address the polysilicon depletion issue in the case of the Wu et al. reference.
A prior art process flow for doping thin layers of polysilicon on thin gate oxides has included the steps of (1) depositing the polysilicon, (2) coating the polysilicon with a resist, (3) exposing the resist, (4) developing the resist, (5) ion implanting phosphorus, (6) ashing the resist, (7) wet cleanup of the resist, (8) coating with resist, (9) exposing the resist, (10) developing the resist, (11) ion implanting boron, (12) ashing the resist, (13) wet cleanup of the resist, and (14) annealing the implant. This process flow requires fourteen major steps.
Phosphorous has not been such an issue at present and is therefore not included in the discussion of the problems addressed herein. However, as the polysilicon gate structure and gate oxide geometries become increasingly thinner, n+ polysilicon doping can become an issue as well.